The present invention relates to a solid-state storage system and a method for controlling the same, and more particularly, to a solid-state storage system for controlling wear leveling flexibly and a method for controlling the same.
In general, nonvolatile memories are widely used as storage memories for portable information devices. Furthermore, in recent years, solid state drives (SSDs) using NAND flash memories, for use in personal computers (PCs) instead of hard disk drives (HDDs), are commercially available, and are expected to make inroads into HDD markets.
Typically, the control of data files in solid-state storage systems such as SSDs is performed by writing, erasing and updating real data in pages designated by logical addresses that can identify the data files. More specifically, a logical address and a physical address of a data storage area are mapped by a Flash Translation Layer (FTL). Then, by referring to the logical address according to a command of a host (not shown), data may be written, erased and read at a location designated by the physical address mapped with the logical address. The physical address is information on the position of a page or a sub block in a memory area.
A NAND flash memory cell is a nonvolatile memory cell. Thus, when updating data of the NAND flash memory cell, the data of the corresponding cell must be first erased and new data must be then programmed. However, data is not programmed uniformly into all memory cells, and may be frequently programmed concentrating on specific cell areas. In other words, due to the frequent data program and erase operations, specific cell areas or some cells may be worn out and may not be used any more. Even though cells having fresh states are present, the entire performance of the solid-state storage system may be limited by the worn cells.
Therefore, before the memory cells are worn out, a wear leveling process for uniform use of the memory cells is performed by changing the physical locations of the storage cells within each memory zone or plane.
In order to execute the wear leveling process, information on the erase counts of all the blocks is stored in the NAND memory area. When the wear leveling process is required, the information on the erase counts of the blocks is loaded into a RAM buffer, and the physical locations of the blocks are changed by searching the replaceable blocks.
However, as the memory area is provided with a larger number of blocks according to the recent large-capacity SSD trend, the memory size of the RAM buffer into which the erase counts of all the blocks are loaded also inevitably increases. However, the increase in the memory size of the RAM buffer is limited by the cost and chip area.